Matrix Vector Multiplier (AXI-Stream) with UART Interface

 

This repository contains the examples for the course: SystemVerilog for ASIC/FPGA Design & Simulation. The examples have been tested on Xilinx Vivado and Synopsys DesignCompiler. Full system, AXI Stream system and their submodules have been tested on Icarus Verilog as well.

 Repo - https://github.com/Vilanjaya/systemverilog